Today, a story of #HOPE for the people of Hillsboro, Oregon, INTEL Corp, and anyone who loves a great comeback story.

The basis of this story came to me from someone with decades of experience and a deep understanding of Intel’s past, which helped me sort through the noise and find the signal.  I am calling him Bagger-Vance, because he taught me, playing the role of Rannulph Junuh, to see The Field. 

Everything about this story might be wrong.  I can not prove any of it. 

But what if the story is right?

Section 1: The Whisper Network: A Semiconductor Giant’s Rumored Resurgence

The relentless march of artificial intelligence dominates headlines, powered by increasingly sophisticated silicon brains. In this narrative, chip designer Nvidia and manufacturer Taiwan Semiconductor Manufacturing Company (TSMC) have emerged as the undisputed leaders, seemingly leaving legacy giant Intel struggling to keep pace. Yet, whispers emanating from the unassuming landscape of Hillsboro, Oregon – home to Intel’s sprawling Ronler Acres campus – suggest a different story is unfolding, one of a potential comeback so audacious it could reshape the technological world order.

This narrative stands in stark contrast to the prevailing sentiment surrounding Intel just nine months ago. Market wisdom, echoed by numerous analysts and industry observers, portrayed a company struggling with manufacturing delays and strategic missteps. Skepticism centered on Intel’s ambitious roadmap, particularly its transition to next-generation process nodes. The cutting-edge High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography tools, considered crucial for future chipmaking, were widely believed to be a distant prospect for Intel, not expected to be production-ready until 2027 for a later node, designated 14A.

Consequently, Intel’s nearer-term 18A node (representing a significant leap comparable to competitors’ 2-nanometer class technology) was largely written off by many external observers. The assumption prevailed that Intel would be forced to rely on existing Low NA EUV technology for 18A, likely employing complex and costly multi-patterning techniques. This approach, it was argued, would put Intel at a disadvantage against TSMC, which had already mastered Low NA EUV, potentially rendering the 18A node uncompetitive or even a “failed node” before it truly began. The idea that Intel CEO Pat Gelsinger might be betting the company’s future on deploying the revolutionary, yet unproven, High NA EUV technology for 18A production as early as 2025 was rarely, if ever, seriously entertained in public discourse.

However, contrarian information from Bagger-Vance paints a dramatically different picture. The core assertion is that Intel’s Ronler Acres facility is not merely meeting its targets but is significantly ahead of the publicly perceived schedule. According to these claims, Intel is already leveraging a potent combination of next-generation technologies – specifically High NA EUV lithography and an advanced chip architecture feature, backside power delivery – for its 18A process. Furthermore, the caddy suggests Intel may have already secured a landmark deal with a titan of the tech world, Microsoft, to manufacture its next-generation AI chips using this very process.

If these claims hold true, the implications are staggering. It would signal a potential turning point for Intel, validating Gelsinger’s aggressive turnaround strategy. More broadly, it could disrupt the current balance of power in the semiconductor industry, challenge Nvidia’s dominance in the AI hardware market, and significantly alter the global chip manufacturing landscape, potentially re-centering cutting-edge production back on American soil far sooner than anticipated. The stakes encompass not just Intel’s corporate future but the very trajectory of the AI revolution itself.

Hillsboro, Oregon, would be the epicenter of that comeback.

Section 2: Decoding the Tech: Intel’s Alleged One-Two Punch

Understanding the potential significance of the developments at Ronler Acres requires an examination of the highly complex world of semiconductor manufacturing. At the heart of the matter lie two key technological advancements Intel is reportedly pioneering with its 18A process: High NA EUV lithography and Backside Power Delivery (BPD).

The Lithography Revolution: High NA EUV Explained

Modern computer chips contain billions of microscopic transistors densely packed onto a small piece of silicon. Creating these intricate patterns involves a process called lithography, which essentially uses light to etch designs onto silicon wafers. For the most advanced chips, manufacturers use Extreme Ultraviolet (EUV) light, which has a very short wavelength, enabling the creation of incredibly small features.

The current standard, Low NA EUV, has been the workhorse for several years. However, as chip features continue to shrink (approaching the 2-nanometer scale and beyond), Low NA EUV faces limitations. To create the finest patterns required for nodes like TSMC’s 2nm process, manufacturers must resort to a technique called multi-patterning. This involves exposing the same layer on the silicon wafer multiple times with the EUV tool, essentially tracing over the intricate pattern several times with slightly shifted masks to achieve the desired resolution. Imagine trying to draw an extremely fine, complex line by carefully overlaying several slightly simpler, thicker strokes. While effective, multi-patterning adds significant complexity, increases the number of manufacturing steps, consumes more time in the extremely expensive EUV machines, raises the potential for errors (yield loss), and ultimately drives up production costs.

This is where High NA EUV enters the picture.  Developed by the Dutch company ASML – the sole global supplier of all EUV lithography machines – High NA EUV represents the next generation of this critical technology. These massive, complex machines, like the 165-ton TWINSCAN EXE:5000 series unit installed at Intel’s Ronler Acres, utilize more advanced optics (a higher Numerical Aperture, hence “High NA”).

This allows them to project significantly finer patterns onto the wafer in a single exposure pass. Think of it as having a much sharper pencil that can draw the intricate line perfectly in one go, eliminating the need for multiple overlapping strokes. Bagger helped me to understand the importance of this.

According to him, the advantage is dramatic. By enabling single-pass patterning for critical layers where Low NA requires multiple passes, High NA EUV is purported to be much more productive for similar devices. At the ASML earnings call, this was confirmed. 

“Intel reported the exposure of more than 30,000 wafers in one quarter and a significant process improvement by reducing the number of process steps from over 40 to less than 10 on a given layer. With that comes a significant cycle time improvement. ” https://ourbrand.asml.com/m/4ab2d65c7edd2a91/original/2025_04_16-ASML-Transcript-investor-call-Q1-2025.pdf

This isn’t just a minor improvement; it represents a potential step-change in manufacturing efficiency. Such a productivity leap could translate directly into faster production cycles, higher wafer output from the fab, and, crucially, a significantly lower manufacturing cost per chip for Intel’s 18A process compared to TSMC’s multi-patterned 2nm process. This potential economic advantage echoes historical shifts in the industry, such as when TSMC gained ground by adopting EUV. At the same time, Intel extended the life of older DUV technology with complex multi-patterning, ultimately losing its process leadership.

Of course, pioneering a brand-new lithography technology like High NA EUV comes with immense challenges. Integrating the tool, developing compatible photoresists and mask technologies, and achieving high production yields are significant hurdles that many observers believed would take years to overcome. The core of Intel’s alleged gamble is that its engineers have managed to tame this complexity far faster than expected.

Powering Up from Below: Backside Power Delivery

Beyond the lithography advancements, Intel’s 18A process reportedly incorporates another key innovation: Backside Power Delivery (BSPDN). BSPDN tackles this problem by moving the power delivery network entirely to the back of the silicon wafer.

Imagine a bustling city where power lines are buried underground in dedicated conduits, freeing up the surface streets entirely for traffic flow. Similarly, BSPDN creates dedicated pathways for power on the underside of the chip, leaving the front side exclusively for optimizing the signal network.

This architectural shift offers several tangible benefits, according to Intel’s public statements and the insider notes.

• Firstly, it reduces electrical resistance and capacitance in the power delivery network, leading to significant power savings, potentially 10-20% lower dynamic power consumption. For power-hungry applications, such as AI, this is a critical advantage.
• Secondly, by improving power delivery integrity and freeing up routing space for signals, BSPDN can enable higher chip performance, potentially a 10-15% increase in operating frequency (clock speed) or throughput at the same power level.
• Thirdly, the improved wiring density allows for greater area efficiency, meaning chip designers can either shrink the overall die size (reducing cost) or pack more functional units like CPU cores or cache memory into the same area, further boosting performance, potentially a 5-10% area advantage.

Crucially, this Backside Power Delivery capability is reportedly a feature of Intel’s 18A node from the outset. At the same time, TSMC’s initial 2nm process (N2) is not expected to include a comparable feature, potentially offering it only in a later variant (N2P). This gives Intel 18A another layer of differentiation, particularly appealing for designers of complex, high-performance, power-sensitive chips – characteristics that define the AI accelerators currently reshaping the computing landscape.

Intel 18A vs. TSMC N2: Key Technology Face-Off

To clarify the core technological distinctions discussed, the following table summarizes the alleged or publicly stated differences between Intel’s 18A and TSMC’s N2 processes:

This comparison highlights the divergent paths being pursued. While TSMC leverages its mastery of the current Low NA EUV paradigm, Intel is making a bold leap to next-generation High NA EUV combined with the architectural innovation of BSPDN. If Intel can successfully execute this strategy on schedule, the combined advantages could indeed present a formidable challenge to the incumbent leader.

Section 3: The Timeline Twist: Did the Market Miss Intel’s Leap?

A crucial element of the potential Intel resurgence centers on timing. As established, the prevailing market narrative until recently held that Intel’s deployment of High NA EUV for high-volume manufacturing was years away, slated for the 14A node around 2027. This timeline underpinned the skepticism surrounding the competitiveness of the earlier 18A node.

However, Mr. Vance’s information directly challenges this timeline, suggesting a significant disconnect between external perception and internal reality, possibly fueled by carefully worded communications from Intel itself. 

Mr. Gelsinger’s reported statement on August 1st, 2024—that “The second High NA tool is coming into our Oregon facility”—fits logically within this sequence. It indicates the arrival process for the second machine started approximately four months after the first machine began its calibration phase. This timing is further corroborated by reports that ASML had initiated the delivery of the second High-NA EUV machine globally on or about April 17, 2024, with Intel widely expected to be the recipient, as the chipmaker had reportedly secured most, if not all, of ASML’s High-NA production output for 2024.

KEY STORY POINT: My source reminded me that ASML, on their April 17, 2024 earnings call, announced with great pride the shipment of their second EXE5000 tool to an undisclosed customer.  Most writers at the time believed that tool went to TSMC or Samsung. About a month later, reports from Korea indicated, with high confidence, that Intel had received the April shipment, quoting Samsung and SK sources.   ASML, on its recent April 2025 earnings call, provided a detailed accounting of the EXE5000s shipped to date, totaling five tools to three different customers. That level of detail indicates with a high probability that Intel has three of those five tools.  One tool was shipped to Oregon in January 2024. Another shipped April 2024 to Chandler. And the third shipped August 2024 to Oregon. The other two tools mentioned by ASML are most likely with Samsung and TSMC, based on reports. Separately, Intel recently confirmed that they have two EXE5000s doing risk production. What is important about the timing and location of these tools is the maturity of Intel in developing its 18A process. A High Volume manufacturing site, Chandler or TD site-D1X Oregon, the location and time frame make a difference in outcomes as Intel ramps production.

Much of this got lost on the casual follower of Intel leading to confusion and outright distrust of Intel on this subject. One point that was not lost on people was the status of Intel’s two new fabs in Chandler: Fab 52 and 62.  Both were making steady progress last year towards completion. Intel CFO David Zinsner on the February 2025 earnings call made a point that Fab 52 was scheduled for its first tool delivery in the near future.  What was missed in all of this and sussed out through research in local Arizona coverage was that one of Pat’s first moves as Intel CEO was to retrofit Fab 42 to accept High NA EUV tools.  The readiness of Fab 42 for High NA EUV was forgotten when Intel announced plans for Fab 52 and 62 with the help of Brookfield partners.

Why does this alleged discrepancy in timing matter so profoundly? If Intel has indeed achieved production readiness for 18A using High NA EUV now, or even several months ago, it means the company is potentially one to two years ahead of the schedule understood by the market for leveraging this game-changing technology at scale. This acceleration fundamentally alters the competitive equation. It suggests that the anticipated cost and productivity benefits of High NA EUV, coupled with the performance advantages of Backside Power Delivery, might be available to Intel and its foundry customers far sooner than rivals expected.

This narrative is diametrically opposed to the current market wisdom about Intel and their potential. It is easy to understand how followers of Intel got wrapped around a different narrative, but when digging deeper on each key data point the potential for this “revised” outcome becomes possible. My source tells me that he’s tried to track every public comment and direct quote regarding 18A and High NA EUV. To him, Intel’s choice of words were always accurate and a fair representation of Intel’s plan at the time. His best guess is that at some point last spring, Intel made the decision to use High NA EUV for some layers of 18A products in 2025. Up until that point, Intel probably had two alternatives they were evaluating. The first option had 18A built on Low NA EUV using 20A as the lead proof point node. When the first High NA EUV tool showed promise building 18A in early wafers and ASML was able to confirm further High NA tool deliveries Intel changed course, pulled the plug on 20A and bet the company on their current direction. And here we are 12 months later with all that we publicly know indicating two High NA EUV tools doing 18A risk start production and 30,000 18A wafers processed.  And a recent Facebook post from an Intel Chandler Fab engineering manager celebrating that the 18A Eagle Had Landed in Chandler Fabs. This post was briefly seen and then removed.  This is a reference to the frequently used “Moonshot” term for impossible tech projects; referencing Kennedy’s call for America to Go to the Moon and Armstrong’s famous pronouncement in 1969. It also placed one of Intel’s High NA EUV tools in Chandler for the first time.

Allowing the market to underestimate its progress could serve as a strategic advantage for Intel. By maintaining a degree of ambiguity around the exact readiness and capability of 18A with High NA EUV, Intel might prevent competitors from reacting too quickly or aggressively. It could also allow Intel to quietly engage with key customers under non-disclosure agreements, securing crucial early commitments for its revitalized foundry business before revealing the full extent of its achievements. This suggests the possibility of a sophisticated information strategy designed to maximize competitive advantage.

Section 4: Ronler Acres: Ground Zero for Intel’s Revolution- Back to Hillsboro

The epicenter of this potential semiconductor earthquake is Intel’s campus in Hillsboro, Oregon, specifically the Ronler Acres location. This sprawling site is not just another manufacturing plant; it represents the heart of Intel’s advanced research and development efforts and is home to some of its most critical fabrication facilities, including the D1X fab, which has long been recognized as a hub for process technology development and high-volume manufacturing ramp-ups.

Ronler Acres cemented its place at the forefront of next-generation chipmaking when it became the recipient of ASML’s very first commercial High NA EUV lithography system, a machine from the TWINSCAN EXE:5000 series. The arrival and installation of this colossal 165-ton tool, costing upwards of $350 million, was a widely reported event, symbolizing Intel’s commitment to regaining process leadership. It is this machine, and potentially a second one now operational, according to the insider claims, that forms the technological bedrock of the alleged 18A production readiness.

However, the story is not just about the hardware. The source emphasized the crucial role of the personnel involved, referring to the “good folks that are the foundation of Ronler Acres” who are poised to “stun the world” with their achievements. This highlights a critical truth often overlooked in discussions of semiconductor technology: possessing the most advanced tools is only half the battle. Operationalizing a revolutionary technology like High NA EUV, integrating it seamlessly into an incredibly complex manufacturing flow involving hundreds of steps, developing the surrounding ecosystem of materials (like photoresists) and metrology (measurement) techniques, and ultimately achieving commercially viable production yields requires extraordinary engineering talent and relentless execution.

Key Story Point: Bringing up a new node, such as 18A, especially one incorporating two major pioneering technologies simultaneously (High NA EUV and BSPDN), involves solving numerous unforeseen challenges. Calibration intricacies, materials science breakthroughs, defect detection and reduction, process control optimization – these are the daily battles fought by the engineers and technicians on the fab floor. The success of Intel’s audacious gamble hinges entirely on the expertise, ingenuity, and perseverance of the team concentrated at Ronler Acres. If Intel is indeed ahead of schedule, it is a testament to this human element – the ability to overcome hurdles previously deemed “technically impossible” by external observers. Ronler Acres, therefore, is not just the location of the advanced machinery; it is the crucible where Intel’s technological future is being forged.

Section 5: Following the Breadcrumbs: Is Microsoft Intel’s Mystery AI Partner?

While achieving technological breakthroughs is essential, realizing their market impact requires customers, particularly large-volume customers for leading-edge nodes. The most tantalizing, and perhaps most speculative, part of the teachings I received from my new friend is the claim that Intel has already secured Microsoft as a flagship customer for its 18A process, specifically for Microsoft’s burgeoning AI chip ambitions. This conclusion is drawn not from direct confirmation, but through a process of deduction based on public statements from key industry players.

The trail begins with Synopsys, a leading provider of Electronic Design Automation (EDA) software crucial for designing complex chips. During its earnings call in February, Synopsys reported strong design activity at advanced nodes, noting that “2-nanometer projects [are] accelerating rapidly.” Crucially, Synopsys mentioned three specific tape-outs – the final stage of chip design before manufacturing begins – in the “2-nanometer” class (a category encompassing both TSMC’s N2 and Intel’s 18A):

1. A “U.S. hyperscaler tape out a 2-nanometer test chip exclusively using Synopsys design flow.”
2. A “U.S. HPC [High-Performance Computing], CPU tape-out.”
3. An “Asian mobile customers 2-nanometer at SOC.” 

Standing alone, this information was ambiguous. However, subsequent comments attributed to AMD, a major competitor in the CPU and HPC space, provided a key piece of the puzzle. AMD CTO Mark Papermaster said the “Venice” chips, expected to ship in 2026, are the “first high-performance product in the industry to be taped out and brought up” on the Taiwanese semiconductor maker’s 2nm node. . Furthermore, industry logic suggests the “Asian mobile customer” is likely MediaTek, another major TSMC client.

This leaves the “U.S. hyperscaler tape out” on a 2 nm-class process. The major US hyperscalers known to be designing their own custom silicon are Amazon Web Services (AWS), Google, and Microsoft. According to Vance’s analysis, recent public updates from AWS (regarding its Trainium and Inferentia chips) and Google (regarding its TPU efforts) make it unlikely that either of them executed a 2 nm-class tape-out fitting the Synopsys description in the January timeframe.

By process of elimination, this points towards Microsoft. If AMD secured the initial US HPC tape-out slot at TSMC for its 2 nm-class chip, and if the remaining US hyperscaler tape-out mentioned by Synopsys also occurred in that timeframe, then Microsoft’s tape-out must have happened at the only other foundry capable of producing such advanced chips: Intel, utilizing its 18A process at Ronler Acres. The chip in question is inferred to be Microsoft’s next-generation Maia AI accelerator, designed to power its vast cloud infrastructure and AI services like Copilot.

Connecting this inference to Microsoft’s broader strategy adds weight to the possibility. Microsoft, under CEO Satya Nadella, has made AI central to its future, investing billions in partnerships (like OpenAI) and internal development. Having a secure supply of cutting-edge, potentially cost-advantaged AI accelerators manufactured domestically would be a massive strategic win. Recent commentary from Microsoft leadership, including former CEO Steve Ballmer and AI chief Mustafa Suleyman, has emphasized the critical importance of silicon innovation for advancing AI capabilities. A partnership with Intel, leveraging the unique purported benefits of 18A (High NA efficiency and BSPDN performance/power), aligns perfectly with these stated ambitions.

While this deductive leap requires confirmation, its implications are immense. Securing Microsoft as the lead customer for 18A would provide Intel Foundry Services (IFS) with instant credibility and the high-volume anchor tenant it needs to succeed. It would signal a powerful strategic alignment between two American tech giants, potentially driven by Intel’s ability to deliver a unique technological package tailored to the demanding needs of AI workloads, developed and manufactured at Ronler Acres.

Section 6: Shifting Tides? A New Era for Chip Supremacy

If the developments unfolding within Intel’s Oregon fabs align with this narrative, the semiconductor industry could be standing at the precipice of a significant power shift. The long-standing dominance of TSMC at the leading edge of manufacturing might face its most serious challenge in years, potentially ushering in a new era of competition and innovation.

The core of this potential disruption lies in the head-to-head comparison between Intel’s 18A and TSMC’s N2 offerings. As outlined previously (see table in Section 2), Intel appears to be betting on a combination of potentially higher manufacturing productivity and lower cost (via single-pass High NA EUV) and superior chip-level performance, power efficiency, and density (via Backside Power Delivery). TSMC, while benefiting from its proven track record and mature Low NA EUV ecosystem, faces the inherent complexities and potential cost overhead of multi-patterning for N2 and will likely only introduce backside power in a later iteration. If Intel can execute 18A successfully and deliver on its promised advantages, it could offer customers like Microsoft a compelling alternative, potentially better performance and lower power consumption at a more competitive price point.

The impact on the booming AI hardware market could be particularly profound. Currently, Nvidia designs the dominant AI GPUs, which are predominantly manufactured by TSMC. A successful Intel 18A process, powering Microsoft’s custom Maia accelerators, would introduce a potent new dynamic. It could provide Microsoft with a vertically integrated solution (design and potentially advantageous manufacturing) to challenge Nvidia’s hardware supremacy more effectively. Furthermore, if Intel’s cost advantages materialize, it could put downward pressure on the currently high prices of cutting-edge AI chips, potentially accelerating AI adoption more broadly.

Beyond specific customers, such a scenario would represent a monumental victory for Intel Foundry Services (IFS), the company’s effort to manufacture chips for external clients. Landing a hyperscale customer like Microsoft for a leading-edge node would instantly validate IFS’s capabilities and erase doubts stemming from Intel’s past manufacturing stumbles. This could open the floodgates for other fabless design companies seeking access to the most advanced technology, transforming IFS from an aspirant into a genuine competitor to TSMC and Samsung Foundry.

The geopolitical context adds another layer of significance. The US government, through initiatives like the CHIPS Act, has made onshore semiconductor manufacturing a national priority. While significant funding is directed towards supporting TSMC’s new fab construction in Arizona, the insider source controversially suggests that Intel’s success in Oregon could render the TSMC Phoenix project “almost meaningless” in the immediate term. This provocative statement likely oversimplifies the long-term strategic importance of diversifying supply chains. However, it highlights a crucial point: if Intel can deliver a more advanced and potentially more cost-effective 2nm-class node (18A) from its existing US facilities sooner than TSMC can ramp up comparable production in Arizona, it could capture the critical initial wave of demand from US companies seeking onshore, leading-edge manufacturing. This would be a major symbolic and practical victory for US technological sovereignty, demonstrating the capability to lead at the absolute cutting edge domestically, potentially shifting the immediate focus from foreign investment to homegrown innovation spearheaded from Ronler Acres.

Section 7: Conclusion: Intel’s Audacious Bet – Poised for Payoff?

The narrative emerging from the whispers around Intel’s Ronler Acres facility presents a compelling, almost cinematic, turnaround story. It suggests a convergence of groundbreaking technological achievements – the accelerated mastery of High NA EUV lithography and the integration of Backside Power Delivery – culminating in a production-ready 18A process far ahead of market expectations. Crowning this achievement is the potential acquisition of Microsoft as a flagship customer, leveraging this advanced Oregon-based manufacturing to fuel its AI ambitions.

If these elements prove accurate, the consequences could be transformative. For Intel, it would mark a stunning return to the forefront of semiconductor manufacturing, validating Pat Gelsinger’s high-risk, high-reward strategy and revitalizing the company’s prospects. For the industry, it could inject fierce competition into the foundry market, potentially recalibrating the dominance of TSMC. In the critical arena of artificial intelligence, it could empower a major new hardware player in Microsoft, potentially altering the competitive landscape currently led by Nvidia. And for the United States, it would represent a significant leap towards securing a domestic supply chain for the world’s most advanced semiconductors.

However, amidst the excitement, a degree of caution is warranted. While the technological aspects regarding High NA EUV and BSPDN are grounded in established physics and engineering principles, the source’s claims regarding the accelerated timeline and, most significantly, the Microsoft partnership, currently rely solely on detailed research and deductive reasoning based on publicly disclosed information. Official confirmation from Intel regarding the specific production status and performance metrics of 18A, and crucially, confirmation from Microsoft regarding its manufacturing plans for future Maia chips, are still required to substantiate this narrative fully.  

All of this might be an impossible shot to make, even if I now clearly see “the field,” which has been so masterfully explained to me by my caddy.

The coming weeks and months will be critical. Industry watchers should pay close attention to upcoming Intel announcements, particularly any disclosures related to 18A progress, High NA EUV deployment, and IFS customer engagements. Microsoft’s future updates on its Maia AI accelerator project will also be revealing. Performance benchmarks of the first 18A-manufactured chips, whenever they emerge, will provide tangible proof of the technology’s capabilities. The data hints that clarity may arrive “over the next few weeks,” suggesting that definitive news might not be far off.

Intel has undeniably placed an audacious bet on its ability to execute complex technological transitions faster and better than its rivals, and faster than most observers thought possible. 

If this new Intel narrative is realistic, all stemming from the incredible work done at Ronler Acres, it is now likely that Intel is on the verge of something truly remarkable. The data indicates that they now possess the tools, process, products, capacity, and customers to change the shape of technology once again.  No doubt that Bob, Andy, and Gordon would all be very proud.

As Bob Noyce once said, “Don’t be encumbered by history; just go out and do something wonderful.”

As for the rest of this story, I am unsure how it will end.  No one does.  But with Bagger’s help, I am going to keep watching The Field, keep listening, and I am going to keep swinging.  For the good people at Hillsboro and at Intel, I hope this is all more than just a dream.

BONUS CONTENT – It was not lost on this writer that the Oregon DEQ issued an updated permit for the Aloha Fab, Oregon’s first facility, last year, which caught my attention.  They did that at the same time that Ronler Acres received approval, almost doubling its previous permit.  Since that permit was issued, the Aloha facility is more active than I have seen it in many years.  After researching this story and looking out across the Silicon Forest with a critical eye (as per Bagger’s instruction), I had to consider whether that could be connected to the suppositions in this story.  It turns out that it could be.

Intel’s Aloha campus in Oregon could not be involved in the fabrication of Microsoft’s Maia AI chips, but it plays a crucial supporting role in Intel’s semiconductor manufacturing ecosystem. The Aloha facility specializes in the final stages of chip production, including advanced packaging and testing processes. These steps are crucial for ensuring the performance and reliability of complex AI chips, such as Maia.

The close proximity of the Aloha and Ronler Acres campuses allows for efficient collaboration between fabrication and packaging teams. As Ronler Acres advances in producing chips using High NA EUV technology, Aloha’s capabilities in packaging and testing become increasingly important. This integrated approach ensures that Intel can meet the demands of clients like Microsoft by delivering high-performance AI chips promptly and reliably.​

The Aloha campus may not be the site of Maia chip fabrication, but its role in the final stages of production is vital. The synergy between Intel’s Oregon facilities positions the company to support the deployment of advanced AI technologies effectively.  This is another sign that my story, and my caddy, are onto something.

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